As the degree of integration of a semiconductor device has recently been increased, the circuit pattern of the transistors or the like included in the semiconductor device increasingly becomes finer. The finer pattern requests not only a reduced line width, but improved dimensional and positioning accuracies of the pattern. This also holds true for the semiconductor memory devices.
Each of the semiconductor memory devices that have been conventionally known and introduced into the market, such as DRAM, SRAM, and a flash memory, uses a MOSFET in the memory cell. Thus, as the pattern becomes finer, the dimensional accuracy is requested to be improved at a ratio higher than that required in fining the pattern. The lithography technology that forms the patterns thus undergoes a large load, which is a factor of increasing the product cost.
As a successor to the semiconductor memory device using the MOSFET as the memory cell, a resistance random access memory has recently drawn attention. In the resistance random access memory, a cross point type cell structure can be adopted. The cross point type cell structure has memory cells formed in intersections of crossing bit-lines and word-lines. The memory cells can thus be made compact more easily than the conventional memory cells, and be stacked in the vertical direction, thereby providing an advantage in that the degree of integration of the memory cell array can be readily improved.
In the semiconductor memory device of the cross point type cell structure, many contacts are formed. The contacts extend in a direction perpendicular to a semiconductor substrate to connect the memory cell array with the peripheral circuits. The contact formation has raised a problem where an open failure is generated at the contact due to some reasons such as poor deposition characteristics of an interlayer dielectric film or insufficient optimization of the interlayer dielectric film in the high densification process or the thermal process. Therefore, there is a need for a structure to suppress the generation of the open failure.